IDENTIFYING DATA 2014_15
Subject (*) COMPUTER ARCHITECTURE Code 17234109
Study programme
Degree of Computer engineering (2010)
Cycle 1st
Descriptors Credits Type Year Period
6 Compulsory Third 1Q
Language
Català
Department Enginyeria Informàtica i Matemàtiques
Coordinator
MOLINA CLEMENTE, CARLOS MARÍA
E-mail carles.aliagas@urv.cat
carlos.molina@urv.cat
Lecturers
ALIAGAS CASTELL, CARLES
MOLINA CLEMENTE, CARLOS MARÍA
Web http://moodle.urv.net
General description and relevant information This course aims to introduce students into the design, implementation and evaluation of superscalar processors and parallel systems.

Competences
Type A Code Competences Specific
 A5 Capacitat per concebre i desenvolupar sistemes o arquitectures informàtiques centralitzades o distribuïdes integrant hardware, software i xarxes.
 A7 Capacitat per definir, avaluar i seleccionar plataformes hardware i software per al desenvolupament i l’execució de sistemes, serveis i aplicacions informàtiques.
 CM9 Capacitat de conèixer, comprendre i avaluar l'estructura i arquitectura dels computadors, així com els components bàsics que els conformen.
 CM14 Coneixement i aplicació dels principis fonamentals i les tècniques bàsiques de la programació paral·lela, concurrent, distribuïda i de temps real.
 CP1 Capacitat per tenir un coneixement profund dels principis fonamentals i models de la computació i saber-los aplicar per interpretar, seleccionar, valorar, modelar i crear nous conceptes, teories, usos i desenvolupaments tecnològics relacionats amb la informàtica.
Type B Code Competences Transversal
Type C Code Competences Nuclear
 C4 Be able to express themselves correctly both orally and in writing in one of the two official languages of the URV

Learning outcomes
Type A Code Learning outcomes
 A5 Dissenya i avalua un processador superescalar
Dissenya i avalua un processador paral.lel
Avalua les tècniques novedoses i avançades d’implementació dels processadors.
Comprèn i aplica el fonaments bàsics de la computació paral·lela
 A7 Dissenya i avalua un processador superescalar
Dissenya i avalua un processador paral.lel
Avalua les tècniques novedoses i avançades d’implementació dels processadors.
 CM9 Dissenya i avalua un processador superescalar
Dissenya i avalua un processador paral.lel
Avalua les tècniques novedoses i avançades d’implementació dels processadors.
Aplica les tècniques d’optimització de programes per a un ús eficient de l’arquitectura.
Comprèn i aplica el fonaments bàsics de la computació paral·lela
 CM14 Comprèn i aplica el fonaments bàsics de la computació paral·lela
 CP1 Dissenya i avalua un processador superescalar
Dissenya i avalua un processador paral.lel
Aplica les tècniques d’optimització de programes per a un ús eficient de l’arquitectura.
Comprèn i aplica el fonaments bàsics de la computació paral·lela
Type B Code Learning outcomes
Type C Code Learning outcomes
 C4 Produce grammatically correct oral texts.
Produce well structured, clear and effective oral texts.
Produce oral texts that are appropriate to the communicative situation.
Produce grammatically correct written texts
Produce well-structured, clear and rich written texts
Produce written texts that are appropriate to the communicative situation

Contents
Topic Sub-topic
1. Evaluation of performance, consumption and cost of processors 1.1. Key concepts: Von Neumann architecture, technologies, trends and challenges.
1.2. Performance: MIPS, MFLOPS, execution time, speedup, benchmarks, Top 500.
1.3. Amhdal's law.
1.4. Consumption: static and dynamic, chip multiprocessors, Green 500.
1.5. Die area and fabrication cost
2. Analysis and design of superscalar processors 2.1. Key concepts.
2.2. Execution model: stages.
2.3. Structures: instruction window, reservation stations, reorder buffer.
2.4. Speculative execution: branches, recovery.
2.5. Interrupts, traps, and exceptions
3. Analysis of parallel processors 3.1. Key concepts.
3.2. Multiprocessor
3.3. Cache coherence.
3.4. Multithread.
3.5. Multicore.
3.6. Other architectures
3.7. Introduction to parallel programming
4. Program optimizations 4.1. Key concepts.
4.2. Sequential optimizations.
4.3. Memory optimizations.

Planning
Methodologies  ::  Tests
  Competences (*) Class hours
Hours outside the classroom
(**) Total hours
Introductory activities
2 0 2
Lecture
A5
A7
CM9
14 20 34
Problem solving, classroom exercises
CM9
CM14
CP1
7 16 23
Laboratory practicals
CM14
CP1
C4
26 40 66
Presentations / expositions
A5
A7
CM9
C4
2 12 14
Personal tuition
2 2 4
 
Extended-answer tests
A5
A7
CM9
CP1
C4
2 0 2
Objective short-answer tests
A5
A7
CM9
C4
2 0 2
Practical tests
CM14
CP1
C4
2 0 2
Oral tests
A5
A7
CM9
C4
1 0 1
 
(*) On e-learning, hours of virtual attendance of the teacher.
(**) The information in the planning table is for guidance only and does not take into account the heterogeneity of the students.

Methodologies
Methodologies
  Description
Introductory activities Description of the objectives, content and assessment process.
Lecture Explanation of theoretical concepts using slides and whiteboard.
Problem solving, classroom exercises Exercises related to the background theory are presented to the students.
Laboratory practicals Application of theoretical knowledge to specific situations, using computers, simulators and other laboratory stuff.
Presentations / expositions Public presentation of a specific topic that extends the concepts introduced in lectures.
Personal tuition Clarification of concepts and solving questions individually

Personalized attention
Description
Professor is available at his office to attend students individually in order to solve any question related to the course.

Assessment
Methodologies Competences Description Weight        
Objective short-answer tests
A5
A7
CM9
C4
Test of short questions where students must show the theoretical knowledge of the subject. 17%
Extended-answer tests
A5
A7
CM9
CP1
C4
Test consisting of problem solving where students will apply theoretical knowledge of the subject. 17%
Practical tests
CM14
CP1
C4
Working in group to develop a project: preliminary analysis, design, implementation and documentation. There will be an individual interview. 33%
Oral tests
A5
A7
CM9
C4
Public presentation of a specific topic that extends the concepts introduced in lectures. 33%
Others  
 
Other comments and second exam session

First call: continuous assessment

Second call: a final exam, an individual project and an individual presentation.


Sources of information

Basic Professors AC, Transparències AC , 2012, DEIM-ETSE-URV
John L. Hennessy i David A. Patterson, Computer Architecture: A Quantitative Approach,, 2006, Morgan Kaufmann
William Stallings, Computer Organization and Architecture: Designing for Performance, 2010, Pearson Education
John Paul Shen, Modern Processor Design: Fundamentals of Superscalar Processors, 2005, McGraw Hill

Complementary Saijan Shiva, Computer Organization, Design, and Architecture, 2008, CRC Press
David Kaeli i Pen-Chung Yew, Speculative Execution in High-Performance Computer Architectures, 2005, Chapman & Hall/CRC
Parhami Behrooz, Computer Architecture: from Microprocessors to Supercomputers, 2005, Oxford University
Harvey Cragon, Computer Architecture and Implementation, 2000, Cambridge

Recommendations

Subjects that continue the syllabus
PARALLEL AND MASSIVE COMPUTING/17234129


Subjects that it is recommended to have taken before
FUNDAMENTALS OF COMPUTERS/17234002
COMPUTER STRUCTURE/17234108
COMPUTERS/17234107
(*)The teaching guide is the document in which the URV publishes the information about all its courses. It is a public document and cannot be modified. Only in exceptional cases can it be revised by the competent agent or duly revised so that it is in line with current legislation.