IDENTIFYING DATA 2014_15
Subject (*) HIGH PERFORMANCE ARCHITECTURES Code 17665102
Study programme
Computer Engineering: Computer Security and Intelligent Systems (2013)
 Cycle 2nd
Descriptors Credits Type Year Period
6 Compulsory First 1Q
Language
Anglès
Department Enginyeria Informàtica i Matemàtiques
Coordinator
MOLINA CLEMENTE, CARLOS MARÍA
 E-mail carles.aliagas@urv.cat
carlos.molina@urv.cat
Lecturers
ALIAGAS CASTELL, CARLES
MOLINA CLEMENTE, CARLOS MARÍA
Web http://moodle.urv.net
General description and relevant information Study of supercomputers (architecture and network), graphic processing units (architecture and programming) and non-general purpose processors (embedded, gaming and phones). Introduction to emerging supercomputing architectures (quantum computing).

Competences
Type A Code Competences Specific
 A1 Project, calculate and design products, processes and installations in all areas of computer engineering.
 A4 Commission, direct and manage manufacture processes for IT equipment, guaranteeing safety for people and goods, the final quality of the products and their approval.
 T6 Design and evaluate operating systems and servers, and applications and systems based on distributed computing.
 T7 Understand and apply advanced knowledge of high performance computing and numerical or computational methods to engineering problems.
 T8 Design and develop computer systems, applications and services in embedded and ubiquitous systems.
Type B Code Competences Transversal
 B1 Learning to learn
 B3 Treballar de forma autònoma amb responsabilitat i iniciativa.
 B4 Comunicar informació, idees, problemes i solucions de manera clara i efectiva en públic o en àmbits tècnics concrets.
Type C Code Competences Nuclear
 C2 Be advanced users of the information and communication technologies
 C4 Be able to express themselves correctly both orally and in writing in one of the two official languages of the URV

Learning outcomes
Type A Code Learning outcomes
 A1 Apply the standard programming model of emerging architectures.
Use the standard programming models in high performance computing.
 A4 Evaluate the performance of a high performance computer.
Evaluate the performance of a high performance interconnection network.
 T6 Are familiar with and understand interconnection network systems at the multicomputer level.
Are familiar with and understand the architecture of multicomputers in supercomputing.
 T7 Evaluate the performance of a high performance computer.
Evaluate the performance of a high performance interconnection network.
Apply the standard programming model of emerging architectures.
Use the standard programming models in high performance computing.
 T8 Apply the standard programming model of emerging architectures.
Type B Code Learning outcomes
 B1 Make significant contributions and be responsible for some innovation.
 B3 Decide how to manage and organize work and the time required to carry out a task on the basis of an initial schedule.
Present results in the appropriate way in accordance with the bibliography provided and before the deadline.
 B4 Analyze, appraise and respond to the questions they are asked during an oral presentation.
Draft documents with the appropriate format, content, structure, language accuracy and register, and illustrate concepts using the appropriate conventions: formats, titles, footnotes, captions, etc.
Prepare their presentations and use a variety of presentation strategies (audiovisual support, eye contact, voice, gesture, time, etc.).
Type C Code Learning outcomes
 C2 Use software for on-line communication: interactive tools (web, moodle, blogs, etc.), e-mail, forums, chat rooms, video conferences, collaborative work tools, etc.
 C4 Produce well structured, clear and effective oral texts.
Produce well-structured, clear and rich written texts

Contents
Topic Sub-topic
1. Introduction to Supercomputing
 1.1. Levels of Parallelism
1.2. Multicomputers and Multiprocessors
1.3. Performance and Consumption
1.4. Top 500 and Green 500
2. General-Purpose Computing on Graphics Processing Units 2.1. GPU Architecture
2.2. GPU Programming
3. High Performance Networks
 3.1. Processor Interconnections
3.2. Supercomputer Networks
3.3. Networks on Chip
4. Non-General Purpose Processors 4.1. Embedded Processors
4.2. Gaming Processors
4.3. Mobile Processors
5. Quantum Computing 5.1. Fundamentals
5.2. Quantum Communication
5.3. Quantum Algorithms
5.4. Current Applications

Planning
Methodologies  ::  Tests
  Competences (*) Class hours
 Hours outside the classroom
 (**) Total hours
Introductory activities
2 0 2
Lecture
A1
A4
T6
T7
T8
 28 22 50
Problem solving, classroom exercises
A1
A4
T6
T7
T8
 4 16 20
Laboratory practicals
B1
B3
C2
C4
 20 28 48
Forums of discussion
B1
B3
C2
C4
 1 24 25
Personal tuition
1 0 1
 
Extended-answer tests
A1
A4
T6
T7
T8
C4
 2 0 2
Objective short-answer tests
A1
A4
T6
T7
T8
C4
 1 0 1
Practical tests
T6
T7
B4
C4
 1 0 1
 
(*) On e-learning, hours of virtual attendance of the teacher.
(**) The information in the planning table is for guidance only and does not take into account the heterogeneity of the students.

Methodologies
Methodologies
  Description
Introductory activities Description of the objectives, content and assessment process.
Lecture Explanation of theoretical concepts using slides and whiteboard.
Problem solving, classroom exercises Exercises related to the background theory are presented to the students.
Laboratory practicals Application of theoretical knowledge to specific situations, using computers, simulators and other laboratory stuff.
Forums of discussion Public discussion among students and professors of a specific topic that extends the concepts introduced in lectures.
Personal tuition Clarification of concepts and solving questions individually

Personalized attention
Description
Professor is available at his office to attend students individually in order to solve any question related to the course.

Assessment
Methodologies Competences Description Weight        
Forums of discussion
B1
B3
C2
C4
 Public presentation of a specific topic that extends the concepts introduced in lectures. 20
Extended-answer tests
A1
A4
T6
T7
T8
C4
 Test consisting of problem solving where students will apply theoretical knowledge of the subject. 25
Objective short-answer tests
A1
A4
T6
T7
T8
C4
 Test of short questions where students must show the theoretical knowledge of the subject. 25
Practical tests
T6
T7
B4
C4
 Working in group to develop a project: preliminary analysis, design, implementation and documentation. There will be an individual interview. 30
Others  
 
Other comments and second exam session

First call: continuous assessment

Second call: a final exam, an individual project and an individual presentation.

Sources of information

Basic Professors AAP, Transparències AAP , 2013, DEIM-ETSE-URV
Parhami Behrooz , Computer Architecture: from Microprocessors to Supercomputers , 2005, Oxford University
Jason Sanders, CUDA by example : an introduction to general-purpose GPU programming , 2011, Addison-Wesley

Complementary Davide Bertozzi, Designing network on-chip architectures in the nanoscale era , 2011, Chapman & Hall/CRC,
Joachim Stolze, Quantum computing : a short course from theory to experiment , 2004, Wiley-VCH
Sundararajan Sriram, Embedded multiprocessors : scheduling and synchronization, 2009, Boca Raton : Taylor & Francis

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(*)The teaching guide is the document in which the URV publishes the information about all its courses. It is a public document and cannot be modified. Only in exceptional cases can it be revised by the competent agent or duly revised so that it is in line with current legislation.