| Competences |
| Type A | Code | Competences Specific |
| A1 | Dissenyar i implementar programari i maquinari per a sistemes electrònics digitals mitjançant dispositius de lògica programable i / o microcontroladors. | |
| Type B | Code | Competences Transversal |
| B5 | Teamwork, collaboration and sharing of responsibility | |
| Type C | Code | Competences Nuclear |
| C4 | Be able to express themselves correctly both orally and in writing in one of the two official languages of the URV |
| Learning outcomes |
| Type A | Code | Learning outcomes |
| A1 |
Valora l'arquitectura i principals característiques de les FPGAs. Dissenya circuits digitals utilitzant un flux de disseny HDL. Dissenya circuits digitals utilitzant un flux de disseny gràfic. Simula i verifica circuits digitals implementats en FPGAs. | |
| Type B | Code | Learning outcomes |
| B5 |
Help to draw up and apply the team’s work processes. | |
| Type C | Code | Learning outcomes |
| C4 |
Produce oral texts that are appropriate to the communicative situation. |
| Contents |
| Topic | Sub-topic |
| Introducction to FPGAs | General architecture Xilinx Spartan-6 |
| VHDL Synthesis | Design flow Entity and architecture Libraries and packages STD y IEEE. Data types RTL description Structural description Behavioral description VHDL synthesis |
| Xilinx System Generator Synthesis | Design flow Representation of real numbers with fixed-point codification Simulink blocks |
| Planning |
| Methodologies :: Tests | ||||||||||
| Competences | (*) Class hours |
Hours outside the classroom |
(**) Total hours | |||||||
| Introductory activities |
|
2 | 0 | 2 | ||||||
| Lecture |
|
20 | 30 | 50 | ||||||
| Laboratory practicals |
|
17 | 30 | 47 | ||||||
| Personal tuition |
|
1 | 0 | 1 | ||||||
| (*) On e-learning, hours of virtual attendance of the teacher. (**) The information in the planning table is for guidance only and does not take into account the heterogeneity of the students. | ||||||||||
| Methodologies |
| Description | |
| Introductory activities | Introduction tutorial to the software tools |
| Lecture | Lectures about the theorical contents |
| Laboratory practicals | Development about the practical contents |
| Personal tuition | Attendances about particular issues |
| Personalized attention |
| Description |
| Attendances in laboratory classes and office |
| Assessment |
| Methodologies | Competences | Description | Weight | ||||
| Lecture |
|
Theorical contents | 50 | ||||
| Laboratory practicals |
|
Developments of contents | 50 | ||||
| Others |
| Other comments and second exam session | |||
|
In the case the laboratories are qualified as deficient, a practical test is assemented |
|||
| Sources of information |
| Basic |
Enrique Cantó, Transparences of the theorical classes, ,
Enrique Cantó, Laboratory guide, ,
Andrew Rushton, VHDL for Logic Synthesis, 3rd Edition, Wiley, 2011
Xilinx, DSP Design Flow, Xilinx, 2013 |
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| Complementary | |||||||||
| Recommendations |
| Subjects that are recommended to be taken simultaneously | ||
|
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(*)The teaching guide is the document in which the URV publishes the information about all its courses. It is a public document and cannot be modified. Only in exceptional cases can it be revised by the competent agent or duly revised so that it is in line with current legislation.