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Type A
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Code |
Competences Specific | | | CE4 |
Dissenyar i implementar programari i maquinari per a sistemes electrònics digitals en l'automòbil, mitjançant dispositius de lògica programable i / o microcontroladors.
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Type B
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Code |
Competences Transversal |
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Type C
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Code |
Competences Nuclear |
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Type A
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Code |
Learning outcomes |
| | CE4 |
Coneix la descripció VHDL dels circuits digitals
Coneix els dispositius FPGA i el flux de disseny HDL
Sap simular i verificar un disseny sobre FPGAs
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Type B
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Code |
Learning outcomes |
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Type C
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Code |
Learning outcomes |
| Topic |
Sub-topic |
| Introducction to FPGAs |
Overview
Spantan-6 architecture: CLB, Routing resources, I/O resources, BRAM, DSP
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| VHDL for synthesis |
Design flow: functional, post-synthesis and post-layout simulation
Entity, architecture, package, package body
Testbench
Libraries: WORK, STD, IEEE
MLV9
RTL, behavioural & structural descriptions
Constants, signals and variables
VHDL Simulation and delta delay
Assertions
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| Methodologies :: Tests |
| |
Competences |
(*) Class hours
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Hours outside the classroom
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(**) Total hours |
| Introductory activities |
|
1 |
0 |
1 |
| Problem solving, exercises |
|
4 |
50 |
54 |
| Personal attention |
|
2 |
0 |
2 |
| |
| Practical tests |
|
2 |
16 |
18 |
| |
(*) On e-learning, hours of virtual attendance of the teacher.
(**) The information in the planning table is for guidance only and does not take into account the heterogeneity of the students. |
Methodologies
| |
Description |
| Introductory activities |
Description of the subject and evaluation |
| Problem solving, exercises |
Set of problems and exercises to be resolved, simulated and submitted |
| Personal attention |
Resolving of doubts about the problems and exercises |
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Description |
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Attendance to students about the contents and proposed exercises |
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Methodologies |
Competences
|
Description |
Weight |
|
|
|
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| Problem solving, exercises |
|
Set of problems and exercises to be resolved, simulated and submitted |
50% |
| Practical tests |
|
Set of questions to be answered, based on a practical exercise |
50% |
| Others |
|
|
|
| |
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Other comments and second exam session |
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| Basic |
E. Cantó, Powerpoint slices, ,
J. Bhasker, A VHDL Primer, 3rd, Prentice Hall
Xilinx, Spartan-6 Family (DS160), ,
Xilinx, Spartan-6 Family (DS160), ,
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|
| Complementary |
J.P. Deschamps, et all, Guide to FPGA implementation of Arithmetic Functions, , Prentice Hall
J.P. Deschamps, Sintesis de Circuitos Digitales. Un Enfoque Algorítmico, , Thompson
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| Subjects that continue the syllabus |
| EMBEDDED SYSTEMS AND COMMUNICATIONS LABORATORY/17695112 | | MASTER'S THESIS/17695301 |
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| Other comments |
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It is necessary to have a previous knowledge about codification of numbers in binary (naturals, A2 complement) and digital circuits (combinational, sequential, FSM) |
(*)The teaching guide is the document in which the URV publishes the information about all its courses. It is a public document and cannot be modified. Only in exceptional cases can it be revised by the competent agent or duly revised so that it is in line with current legislation. |
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