Tema Subtema
Introducció a les FPGAs Overview
Spantan-6 architecture: CLB, Routing resources, I/O resources, BRAM, DSP
VHDL per sintesi Design flow: functional, post-synthesis and post-layout simulation
Entity, architecture, package, package body
Testbench
Libraries: WORK, STD, IEEE
MLV9
RTL, behavioural & structural descriptions
Constants, signals and variables
VHDL Simulation and delta delay
Assertions